1. Field of the Invention
This invention is related to the field of design testing, more specifically to the design of a scan latch for which scan may be enabled in either clock phase.
2. Description of the Related Art
Design testability plays an important role in integrated circuit (IC) design, since it facilitates discovering defects that may be present in the fabricated circuit. One of the most common methods for delivering test data from IC inputs to the internal circuitry being tested is through a methodology called scan design. Scan design allows shifting in test data through the input pins of the IC, and detecting defects by observing data returned on output pins of the IC. The scan process is implemented through special registers called scan registers (also referred to as scan flops and scan cells), which are connected in one or more scan chains that are used for gaining access to various internal nodes and functional logic portions of the IC. Most of the time a scan flop is designed having both shift and parallel-loading capability, and may include a number of storage cells or latches to be used as observation points and/or control points. Scan flops therefore enhance observability and/or controllability of a circuit during the testing process.
When performing a scan test, the scan flops are typically controlled by an additional signal called a scan enable (SE) signal. Using the SE signal, scan flops in the IC, or in a given designated portion of the IC, can be operated together as a long shift register, with data provided to the shift register through a designated input pin(s) of the IC, and data read from the shift register through a designated output pin(s) of the IC. Test patterns can be shifted in via the scan chain(s), using the IC's clock signal or functional clock signals within the IC to clock the shifting process, as well as the capture of the test data. Once the data has been shifted in, the test itself is performed during what is referred to as a “scan cycle” or “capture cycle”. The capture cycle is initiated by changing the value of the SE signal, resulting in the capture of data from the internal circuitry being tested. The value of the SE signal is then changed back to shift out the results to the designated output pin(s). The test that has been thus obtained can then be compared against expected results.
While there is some degree of freedom in how scan operations for a given IC are performed, and how scan flops are structured, scan flop designs are oftentimes influenced by a multitude of factors, and a great variety of scan flop designs and scan flop clocking techniques exist. In order to gain advantage in some areas, constraints may have to be imposed in other areas. For example, in some scan flops the SE signal is restrained to be operated as a low-phase (of the clock) signal in order for the scan flop and the scanning process to function correctly. That is, the SE signal can only be asserted to initiate the capture cycle (or scan cycle) during a low phase of the clock, which imposes an undue limit on the use of the SE signal.